(A) Field of the Invention
The present invention relates to an equalizer circuit, and more particularly, to a transversal filter circuit.
(B) Description of the Related Art
Equalizer circuits, also known as equalization filter circuits, which can adjust the frequency response of an input signal, are often applied in digital circuits to reduce the signal noise, enhance the signal accuracy or generate a new signal. A basic digital equalization operation multiplies the frequency responses of an equalizer and an input signal to obtain a new signal, wherein the corresponding operation in time-field is the convolution operation. A convolution operation can be described as
            y      ⁡              [        n        ]              =                  ∑                  k          =          0                          m          -          1                    ⁢                        w          ⁡                      [            k            ]                          ⁢                  x          ⁡                      [                          n              -              k                        ]                                ,wherein x[n] is an input signal, y[n] is an output signal, w[n] represents the coefficients of the digital equalization operation in time-field and m is the number of coefficients. A transversal filter circuit is the implementation of the convolution operation, comprising a plurality of delay units, a plurality of multipliers and a plurality of adders. The delay units provide a plurality of input signals x[n] to x[n−m+1]. The multipliers multiply the coefficients of the digital equalization operation and the plurality of input signals. The adders accumulate the products outputted by the multipliers.
In the IEEE 802.3 100 BASE-TX standard, a structure of decision feedback equalizer is utilized to deal with the inter-symbol interference (ISI) problem. FIG. 1 shows the block diagram of a conventional decision feedback equalizer 100. The decision feedback equalizer 100 comprises a feed forward filter 110, a feedback filter 120, an adder 130 and a detector 140, wherein the feed forward filter 110 and the feedback filter 120 are both transversal filters. The adder 130 subtracts a previously determined output signal from a presence signal so that the noise in the presence signal caused by the remaining previous signal is eliminated. The detector 140 then determines the output signal.
FIG. 2 shows the block diagram of a conventional transversal filter applied as a feedback filter in a decision feedback equalizer. The transversal filter 200 comprises a plurality of delay units 210, a plurality of multiplexer 220, a plurality of first-level adders 230, a plurality of second-level adders 240 and a plurality of inverters 250. Applying the IEEE 802.3 100 BASE-TX standard, the input signal of the transversal filter 200 is a two-bit signal with “multi-level transmit with 3 voltage levels” (MLT-3) representation. That is, the value of the input signal of the transversal filter 200 is 2′b00, 2′b01 or 2′b10, representing 0, 1 and −1 respectively. The transversal filter 200 corresponds to a convolution operation
            y      ⁡              [        n        ]              =                  ∑                  k          =          0                          m          -          1                    ⁢                        w          ⁡                      [            k            ]                          ⁢                  x          ⁡                      [                          n              -              k                        ]                                ,wherein m is the number of delay units 210, x[n] is represented by xn and w[n] is represented by wn in FIG. 2. As shown in FIG. 2, since the value of the input signal of the transversal filter 200 is either 0, −1 or 1, the multiplication operation can be achieved by the plurality of multiplexer 220. When one of the input signals xk is 0, the corresponding multiplexer 220 outputs 0. When one of the input signals xk is 1, the corresponding multiplexer 220 outputs the corresponding coefficient wk. When one of the input signals xk is −1, the corresponding multiplexer 220 outputs the corresponding coefficient −wk. The coefficients w[n] are usually multi-bit numerals, such as 8-bit numerals, and are often represented by 2's complement representation. Therefore, the representation of −wk is implemented by taking the complement of each bits of wk, and adding this numeral to 1. The first-level adders 230 and the inverters 250 achieve the aforesaid inversion operation.
For the transversal filter 200 with a total of m coefficients w[n], it requires a total of m first-level adders 230. In addition, the transversal filter 200 also requires a total of m−1 second-level adders 240 to accumulate the output signals of the multiplexers 220. As a result, the transversal filter 200 requires a total of 2m−1 adders, which does not meet the requirement of small circuit area and low cost for modern digital circuit design.